Digitally calibrated successive approximation analog to digital converters (ADC), are now well known. To avoid missing codes in such ADCs, some form of error correction is required within a digital to analog converter, DAC, provided therein. This may take the form of radix less than 2 bit weights, additional error correction bits, or other forms of redundancy.
In an uncorrected traditional SAR converter, the final result is the sum of the ideal kept bit weights. For example, for a 6 bit converter which outputs the result 101011, the value of this result is taken as being 32+8+2+1=43. But suppose that for this converter we know that the actual bit weights are 32.5, 16.0, 8.4, 4.0, 2.1 and 1. A digitally corrected converter determines the final result by adding together the real weights of the kept bits 32.5+8.4+2.1+1=44 and then outputting the appropriate digital value representative of that result. The final result digitally corrected binary result is then 101100.
As mentioned above, a digitally corrected ADC does need some form of redundancy to avoid errors. To demonstrate this, consider the case where a 6 bit ADC has bit weights of 33, 16,8,4,2 and 1, i.e. the most significant bit is overweight by one least significant bit, LSB. Let's assume that the input is equivalent to a bit weight of say 32.9. The value of 33 would be rejected in the 1st bit trial as the weight of 33 is larger than 32.9. All the subsequent bits would be kept giving a value of 16+8+4+2+1=31. This is in error by 1.9. To avoid this, redundancy is required of the same magnitude as the maximum total error of any combination of kept bits. For the above case we may want to add a redundant bit of weight 1 giving a DAC with weights 33,16,8,4,2,1,1. Now, after the MSB bit is rejected all the following bits are kept, including the additional redundant bit, giving a weight of 16+8+4+2+1+1=32. Now the error is reduced to 0.9 LSB, which is within the resolution of the converter.
A particularly important specification for an ADC is differential non-linearity known as DNL. This can be defined as the difference between the actual and the ideal code width of a converter code relative to the ideal code width (which is 1LSB). It is important to note that digital correction is a post processing activity. It is does not affect the operation of the analog part of the ADC at all. Hence transitions between codes occur at the same place for an analog ADC as for the same ADC with digital correction applied. This is a limitation of digitally corrected ADCs. Another important specification for an ADC is integral non-linearity known as INL. INL can be defined as the deviation from a straight line passing through the endpoints of the ADC transfer function. Digital correction will improve the INL of an ADC.